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Naresh Kumar Reddy

Dr. Naresh Kumar Reddy

Assistant Professor

Dr. Naresh Kumar Reddy is an Assistant Professor in the School of Electronic Systems and Automation, Digital University Kerala (Former IIITM-Kerala), India. Prior to joining DUK, he was with the Department of Electrical Engineering, Indian Institute of Technology Delhi, India as a Post-Doctoral Fellow. He received his B.Tech. (in Electronics & Communication Engineering) from Sri Venkateswara University in the year 2010 and M. Tech. (in Embedded Systems) from K.L.University in the year 2012 respectively. His higher education includes full-time Ph.D. (Engg.) research supported by Visvesvaraya Ph.D. Scheme, Government of India at National Institute of Technology, Goa, which got completed in the year 2018. He has also spent with Intel Technology India Pvt. Ltd., Bangalore, as the Graduate Intern Technical. Dr. B. Naresh Kumar Reddy is currently involved in various teaching/research-related areas like networks-on-chip, design methodologies for system-on chip, VLSI and embedded systems. He is a member of IEEE and ACM.

Google Scholar ID: https://scholar.google.co.in/citations?user=HSqqGF4AAAAJ&hl=en

Scopus ID: https://www.scopus.com/authid/detail.uri?authorId=56038481700

ORCID ID: https://orcid.org/0000-0001-8434-3673

DBLP: https://dblp.org/pid/140/8798.html

Recent Publications List (Last 5 years)

International Journals:

  • Springer (Published): B. Naresh Kumar Reddy, “Design and implementation of high performance andarea efficient square architecture using Vedic Mathematics," Analog Integr Circ Sig Process, Vol 102, pp. 501-506, 2020. (Impact Factor= 1.337)
  • Springer (Published): B. Naresh Kumar Reddy, B. Veena Vani and Bhavya Lahari “ An efficient design and implementation of Vedic multiplier in quantum-dot celluar automata," Telecommunication Systems (TELS), 2020. (Impact Factor= 2.314)
  • Springer (Published): Shakeel Ahmed, N. V. K. Ramesh and B. Naresh Kumar Reddy, “A Highly Secured QoS Aware Routing Algorithm for Software Defined Vehicle Ad Hoc Networks Using Optimal Trust Management Scheme," Wireless Personal Communications, 2020. (Impact Factor= 1.671)
  • Springer (Published): V Javvaji, S Musala, B. Naresh Kumar Reddy, “Continuous-time complex band-pass Gm-C sigma delta ADC with programmable bandwidths," Analog Integr Circ Sig Process, Vol 108, pp. 267-276, 2020. (Impact Factor= 1.337)
  • Springer (Published): B. Naresh Kumar Reddy, Dharavath Kishan and B. Veena Vani“Performance constrained multi-application network on chip core mapping," International Journal of Speech Technology , 2019.
  • Elsevier (Published): B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “An EnergyEfficient Fault-Aware Core Mapping in Mesh-based Network on Chip Systems,” Journal of Network and Computer Applications, Vol. 105, pp. 79-87, 2018. (Impact Factor= 6.281)
  • Elsevier (Published): B. Naresh Kumar Reddy, Vasantha.M.H., and Nithin Kumar Y.B., “System Level Fault-Tolerance Core Mapping and FPGA-based Verification of NoC," Microelectronics Journal, Vol. 70, pp. 16- 26, 2017. (Impact Factor= 1.605)
  • Elsevier (Published): B. Naresh Kumar Reddy, Vasantha.M.H., and Nithin Kumar Y.B., “High- Performance and Energy-Efficient Fault-Tolerance Core Mapping in NoC,” Sustainable Computing, Informatics and Systems, Vol. 16, pp. 1- 10, 2017. (Impact Factor= 4.028)
  • Springer (Published): B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “Hardware Implementation of Fault Tolerance NoC Core Mapping,” Telecommunication Systems (TELS), Vol 68, pp. 621- 630, 2017. (Impact Factor= 2.314)
  • Springer (Published): B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “Energy Aware and Reliability- Aware Mapping for NoC-Based Architectures,” Wireless Personal Communications, Vol. 100, pp. 213- 225, 2017. (Impact Factor= 1.671)
  • Springer (Published): B. Naresh Kumar Reddy, C Ramalingaswamy, R Nagulapalli, D Ramesh,“A novel 8T SRAM with improved cell density,” Analog Integr Circ Sig Process, Vol. 98, Issue 2, pp. 357-366, 2018. (Impact Factor= 1.337)
  • Springer (Published): Chintala Yehoshuva, B. Naresh Kumar Reddy, Venkata Reddy Ambati, Suresh Kumar Pittala, “A novel CMOS GmC complex lter design for multi-mode multiband wireless receiver applications,” Analog Integr Circ Sig Process, Vol. 91, Issue 1, pp. 43-51, 2017. (Impact Factor= 1.337)
  • IET (Published): Ramalingaswamy Cheruku, Damodar Reddy Edla, Venkatanareshbabu Kuppili, Ramesh Dharavath and B. Naresh Kumar Reddy, “Automatic Disease Diagnosis using Optimized Weightless Neural Networks for Low-Power Wearable Devices,” IET Healthcare Technology Letters, Vol. 4, Iss. 4, pp. 122–128, 2017.

International Conferences:

  • Sudheer H, G Sai Vishal Reddy and B Naresh Kumar Reddy, “Design and Analysis of High Reliable Fault Tolerance Subsystem for Micro Computer Systems,” 11th IEEE Symposium on Computer Applications & Industrial Electronics ( ISCAIE 2021), Penang, Malaysia , pp. 127-130, 2021.
  • Sai Kumar, T.V.K.Hanumatha Rao and B. Naresh Kumar Reddy, “Exact Formulas for Fault Aware Core Mapping on NoC Reliability,” 17th International IEEE India Conference INDICON, 2020.
  • B Naresh Kumar Reddy, G Sai Vishal Reddy, B Veena Vani, “Design and Implementation of an Efficient LFSR using 2-PASCL and Reversible Logic Gates,” IEEE Bombay Section Signature Conference (IBSSC), pp. 247-250, 2020.
  • B. Naresh Kumar Reddy, K Sarangam, T Veeraiah, R Cheruku , " SRAM cell with better read and Write stability with Minimum area," IEEE Region 10 Conference (TENCON), 2164-2167, 2019.
  • B. Naresh Kumar Reddy, and B. Sireesha, “An Efficient Core Mapping Algorithm on Network on Chip,” 22nd International Symposium on VLSI Design and Test (VDAT), 2018.
  • Ramalingaswamy Cheruku, Pradeep Kumar Nalluri, Gopi Krishna Yogeshwar G., J.B.S. Charan, Naga Sanketh V., and Naresh Kumar Reddy Beechu, "A Bi-Level Cascaded Ensemble Framework for Effective Disease Diagnosis," IEEE Region 10 Conference (TENCON), 2065-2068, 2019.
  • R. Nagulapalli1, K. Hayatleh, S. Barker, B. Naresh Kumar Reddy, " A High Frequency CMRR improvement technique for Differential Amplifiers in 45nm CMOS ", 10th ICCCNT 2019, IIT Kanpur, India.
  • R. Nagulapalli1, K. Hayatleh, S. Barker, B. Naresh Kumar Reddy, " A Low Power Miller Compensation Technique for Two Stage Op-amp in 65nm CMOS Technology", 10th ICCCNT 2019, IIT Kanpur, India.
  • R. Nagulapalli1, K. Hayatleh, S. Barker, S. Zourob, N. Yassine, and B. Naresh Kumar Reddy, " A 31 ppm/◦C Pure CMOS Bandgap Reference by Exploiting Beta-Multiplier", 22nd International Symposium on VLSI Design and Test (VDAT), 2018.
  • R. Nagulapalli1, K. Hayatleh, S. Barker, S. Zourob, N. Yassine, and B. Naresh Kumar Reddy, " High Performance Circuit Techniques for Nueral Front-End design in 65nm CMOS", 9th ICCCNT 2018, IISC, Bengaluru, India.
  • R. Nagulapalli1, K. Hayatleh, S. Barker, S. Zourob, N. Yassine, and B. Naresh Kumar Reddy, " A Technique to Reduce the Capacitor size in Two Stage Miller compensated opamp ", 9th ICCCNT 2018, IISC, Bengaluru, India.
  • V Narendar, Shrey and B. Naresh Kumar Reddy, “Performance Enhancement of Multi-Gate MOSFETs Using Gate Dielectric Engineering ,” International Conference on Computing, Power and Communication Technologies (GUCON), India. 2018.
  • B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare core,” 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2016), Pennsylvania, U.S.A., pp. 146-151, 2016.
  • Vijaya Sree Boddu, B. Naresh Kumar Reddy and M. Kranthi Kumar, “Low-Power and Area Efficient N-bit Parallel Processors on a Chip,” 13th International IEEE India Conference INDICON 2016, pp. 1-4, 2016.
  • B. Naresh Kumar Reddy, Vasantha.M.H., Nithin Kumar Y.B. and Dheeraj Sharma, “Communication Energy Constrained Spare Core on NoC,” 6th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Dallas, U.S.A., pp. 1-4, 2015.
  • B. Naresh Kumar Reddy, Vasantha.M.H., Nithin Kumar Y.B. and Dheeraj Sharma, “A Fine Grained Position for Modular Core on NoC,” IEEE International Conference on Computer, Communication and Control, Sep 2015.
  • B. Naresh Kumar Reddy, N. Suresh, J. V. N. Ramesh, T. Pavithra, Y. Krupa Bahulya, Pranose J Edavoor and S. Janaki Ram, “An Efficient Approach for Design and Testing of FPGA Programming using LabVIEW,” 4th International Conference on Advances in Computing, Communication and Informatics, Aug 2015.
  • G S Ajay Kumar Reddy, S. V. Jagadesh Chandra and B. Naresh Kumar Reddy, “Developing the fabricated system of automatic vehicle identification using RFID based poultry traceability system,” International Conference on Information Communication and Embedded Systems, pp. 1-6, 2014.
  • B. Naresh Kumar Reddy, M. Naraimhulu, S. V. Sai Prasad, K. Khaja Babu and S. V. Jagadeesh Chandra, “An Efficient Online Mileage Indicator by Using Sensors for New Generation Automobiles,” IEEE Bangalore Section technically co-sponsor on 2nd International Conference on Advanced Computing, Networking and Security, pp. no. 198-203, Dec, 2013.

Patent

  • “A Scalable and Energy- Efficient Fault Tolerant Network on Chip ”. Application Number: 202041030007 A, 2020. Application Status: Published and Awaiting for Technical Examination.